A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Cut layers for an integrated circuit design are the metal plugs that connect two metal routing layers. Cut shapes must be connected to metal above and below the cut on the IC. This sandwich of two metal pieces and the cut (metal connecting the two shapes) is commonly called a “via.”
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may uses a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
Photolithography is a fabrication process by which patterns for various devices, such as integrated circuits, are generated on substrate wafers. This process generally starts with the design of an IC chip, including the various circuit elements, their electrical interconnects, and their physical layout across the chip. After an integrated circuit is designed, a photomask is created. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. A typical photolithography system projects UV light energy on to and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer.
The resolution limit of conventional optical lithography technology is increasingly being challenged by the sub wavelength, or low-kl, dimensions of the critical IC feature geometries. Not only are the critical dimension feature geometries decreasing in size in accordance with, or even faster than, Moore's Law predictions, the already large number of these feature geometries is growing at a dramatic rate as well. Furthermore, due to the necessity to mitigate optical proximity effect distortions through resolution enhancement techniques at the mask level, the overall polygonal figure count is skyrocketing. These critical feature geometries are patterned far more precisely as well due to the severity and sensitivity of the non-linear imaging. Extreme precision is required for sub wavelength, or low-kl, applications due to highly non-linear imaging behaviors which often magnify mask errors by large factors and non-intuitive manners.
With the overall year-to-year increase in IC logic function, industry trends towards larger and more complex system-on-chip and mixed signal designs, and increasingly aggressive use of artificial layout enhancement for manufacturability (LEM) features such as Resolution Enhancement Technology (RET), Optical Proximity Correction (OPC), and dummy fill patterns, IC physical design layout data volume and resulting mask data file volume sizes are exploding. Using “scatter” or “scattering” bars is an example of such enhancement techniques. A scattering bar is an additional design element, below the resolution of the lithography process, which is placed near another object to enhance the edge quality of that nearby object.
In deep submicron design a significant amount of time and effort is usually spent dealing with design manufacturability rules, such as via rules. A two step process may be employed to handle via rules. First, different via configurations are identified. Second, a large amount of time is spent generating scatter bars around the via.
To illustrate how scattering bars may be generated in conventional tools, consider the via 100 shown in FIG. 1a. The first step to determining a configuration of scattering bars for a via is to perform a “size” operation around the via 100 with the boundary 102 as shown in FIG. 1b. The next step is to perform a spacing operation between the via 100 and the edge of the outer boundary 102 with spacing elements 104a-d as shown in FIG. 1c. Another sizing operation is then performed within the inner boundary 106 as shown in FIG. 1d. 
A logical NOT operation is performed between the shapes in this example to reveal the scattering bars 108a, 108b, 108c, and 108d as shown in FIG. 1e. The final configuration 110 of the scattering bars 108a-c around the via 100 is as shown in FIG. 1f. 
The problem with this approach is that there is usually a very large number of vias in a design, potentially on a large number of layers. If each via in the design requires this number of actions to process that via, then an inordinate amount of time may be consumed just to handle this type of processing for scattering bars.
The problem is further exacerbated by additional steps that must be taken to address multiple-via combinations. To explain, consider the via combination 202 having vias 204 and 206 shown in FIG. 2a. Using the above process, this via combination 202 may result in the configuration of scattering bars 200a-e shown in FIG. 2b. 
In this example, an extraneous scatter bar 200a would have been generated between the two vias. The EDA tool would eliminate the unneeded scattering bar 200a as shown in FIG. 2c. 
The problem is that the system would necessarily need to take additional processing operations to find and eliminate all such extraneous scatter bars in the design. If there is a large number of via combinations in the design(and different configurations of such combinations), then a significant amount of resources would have to be additionally expended to handle this problem, which would negatively affect the performance of the EDA tool.
In addition to the above, part of DRC operations is to check the correctness of scattering bars, e.g., for distance and dimensions. In addition, correctness of scattering bars to neighboring scattering bars must be checked.
Therefore, there is a need for improved techniques to handle design and manufacturability rules and to implement layout enhancement techniques for IC designs. Some embodiments of the invention pertain to an improved approach for processing design objects, such as vias, for an integrated circuit design. In some embodiments, pattern matching is employed to perform DRC/LVS for scattering bars and Vias. In addition, in some embodiments, a library of via combinations is used to insert scattering bars into design. This approach of using a library can be applied to other structures in design in addition to vias.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.